As you build your IC layout, you want to ensure that it does what it is meant to do. You want to perform a valid and complete extraction so you can verify your results through simulations and by comparing the extracted netlist with the original one.

dw-2000 HLVS provides designers with an efficient tool for detecting network mismatches occurring in the physical layout. It consists of an HLE component that outputs a netlist based on extracted hierarchical and generic devices, including their parameters and parasitics, and of an LVS component that compares two SPICE netlists.

The Hierarchical Layout Extractor (HLE) Module

HLE uses the physical geometric organization of a circuit layout and translates it into an electrical network (or netlist). Based on user-defined relationship information, it proceeds to detect electrical components from the geometrical relationships of the layout. HLE then generates a netlist in HSPICE format. HLE is capable of extracting:

• All common devices such as: MOSFETS transistors, BJT transistors, diodes, capacitors and resistors
  
• Generic user-defined devices
  
• Parisitics (capacitors and resistors).

HLE provides the designer the ability to perform hierarchical extraction; the designer defines which nested Structures to instantiate as "leaf cells" in the netlist. This powerful feature allows the layout hierarchy to be different than the reference netlist hierarchy, thereby freeing you from having to apply the same hierarchy in your layouts. HLE provides a collection of GPE commands, ranging from basic extraction control and display functions to specific details of extraction. HLE also provides advanced commands for creating and manipulating devices and other elements. These commands allow you to adapt the extractor to highly specific tasks.

dw-2000 HLVS includes a network navigator that allows you to view extracted layouts. Designers can query information about a particular active element or simply highlight a particular net.

The Layout versus Schematic (LVS) Module

The LVS produces an easy to understand report, which lists all sources of discrepancies it detects between the layout generated netlist and the original netlist. Designers can specify options and tolerance values in order to allow for acceptable differences between the two netlists. Name binding files are used to compare netlists that do not have symmetrical cell representations.

The LVS report, combined with the extracted view provides designers with an efficient mechanism for locating mismatches in the netlist.